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1 of 12 110602 features 10 years minimum data retention in the absence of external power data is automatically protected during power loss power supply monitor resets processor when v cc power loss occurs and holds processor in reset during v cc ramp-up battery monitor checks remaining capacity daily read and write access times as fast as 70ns unlimited write cycle endurance typical standby current 50 a upgrade for 512k x 8 sram, eeprom, or flash lithium battery is electrically disconnected to retain freshness until power is applied for the first time full 10% v cc operating range (ds1350y) or optional 5% v cc operating range (DS1350AB) optional industrial temperature range of -40 c to +85 c, designated ind powercap module (pcm) package - directly surface-mountable module - replaceable snap-on powercap provides lithium backup battery - standardized pinout for all nonvolatile (nv) sram products - detachment feature on powercap allows easy removal using a regular screwdriver pin assignment pin description a0 ? a18 - address inputs dq0 ? dq7 - data in/data out ce - chip enable we - write enable oe - output enable rst - reset output bw - battery warning v cc - power (+5v) gnd - ground description the ds1350 4096k nv srams are 4,194,304 bit, fully static, nv srams organized as 524,288 words by 8 bits. each nv sram has a self-contained lithium energy source and control circuitry, which constantly monitors v cc for an out-of-tolerance condition. when such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. additionally, the ds1350 devices have dedicated circu itry for monitoring the status of v cc and the status of the internal lithium battery. ds1350 devices in the powercap module package are directly surface mountable and are normally paired with a ds9034pc powercap to form a complete nv sram module. the devices can be used in pl ace of 512k x 8 sram, eeprom or flash components. ds1350y/ab 4096k nonvolatile sram with battery monito r www.maxim-ic.com 1 bw 2 3 a15 a16 rst v cc we oe ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 4 5 6 7 8 9 10 11 12 13 14 15 16 17 a 17 a 14 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 a 13 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 34 a 18 gnd v bat 34-pin powercap module (pcm) ( uses ds9034pc powerca p)
ds1350y/ab 2 of 12 read mode the ds1350 devices execute a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) and oe (output enable) are active (low). the uniqu e address specified by the 19 address inputs (a 0 -a 18 ) defines which of the 524,288 bytes of data is to be accessed. valid data will be available to the eight data output drivers within t acc (access time) after the last addre ss input signal is stable, providing that ce and oe (output enable) access times are also satisfied. if oe and ce access times are not satisfied, then data access must be measured from the later-occurring signal ( ce or oe ) and the limiting parameter is either t co for ce or t oe for oe rather than address access. write mode the ds1350 devices execute a write cycle whenever the we and ce signals are in the active (low) state after address inputs are stable. the later-occurring falling edge of ce or we will determine the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control signal should be kept inactive (high) during write cycles to avoid bus contention. however, if the output drivers are enabled ( ce and oe active) then we will disable the outputs in t odw from its falling edge. data retention mode the DS1350AB provides full functional capability for v cc greater than 4.75v and write protects by 4.5v. the ds1350y provides full functional capability for v cc greater than 4.5v and write protects by 4.25v. data is maintained in the absence of v cc without any additional support circuitry. the nv srams constantly monitor v cc . should the supply voltage decay, the nv srams automatically write protect themselves, all inputs become ?don?t care,? and all outputs become high-impedance. as v cc falls below approximately 2.7v, the power switc hing circuit connects the lithium energy source to ram to retain data. during power-up, when v cc rises above approximate ly 2.7v, the power switching circuit connects external v cc to the ram and disconnects the lithium energy source. normal ram operation can resume after v cc exceeds 4.75v for the DS1350AB and 4.5v for the ds1350y. system power monitoring ds1350 devices have the ability to monitor the external v cc power supply. when an out-of-tolerance power supply condition is detected, the nv srams wa rn a processor-based system of impending power failure by asserting rst . on power-up, rst is held active for 200ms nominal to prevent system operation during power-on tran sients and to allow t rec to elapse. rst has an open drain output driver. battery monitoring the ds1350 devices automatically perform periodi c battery voltage monitoring on a 24-hour time interval. such monitoring begins within t rec after v cc rises above v tp and is suspended when power failure occurs. after each 24-hour period has elapsed, the ba ttery is connected to an internal 1m test resistor for one second. during this one second, if ba ttery voltage falls belo w the battery voltage trip point (2.6v), the battery warning output bw is asserted. once asserted, bw remains active until the module is replaced. the battery is still retested after each v cc power-up, however, even if bw is active. if the battery voltage is found to be higher than 2.6v during such testing, bw is de-asserted and regular 24-hour testing resumes. bw has an open drain output driver.
ds1350y/ab 3 of 12 packages the 34-pin powercap module integrates sram memo ry and nonvolatile control along with contacts for connection to the lithium battery in the ds9034pc powercap. the powercap module package design allows a ds1350 pcm device to be surface mounted without subjecting its lithium backup battery to destructive high-temperature reflow soldering. after a ds1350 pcm is reflow soldered, a ds9034pc is snapped on top of the pcm to form a complete nonvolatile sram module. the ds9034pc is keyed to prevent improper attachment. ds1350 powercap modules and ds9034pc powercaps are ordered separately and shipped in separa te containers. see the ds9034pc data sheet for further information.
ds1350y/ab 4 of 12 absolute maximum ratings* voltage on any pin relativ e to ground -0.3v to +7.0v operating temperature range 0c to 70c, -40c to +85c for ind parts storage temperature range -40c to + 70c, -40c to +85c for ind parts soldering temperature 260c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (t a : see note 10) parameter symbol min typ max units notes DS1350AB power supply voltage v cc 4.75 5.0 5.25 v ds1350y power supply voltage v cc 4.5 5.0 5.5 v logic 1 v ih 2.2 v cc v logic 0 v il 0.0 0.8 v dc electrical (v cc = 5v 5% for DS1350AB) characteristics (t a : see note 10) (v cc = 5v 10% for ds1350y) parameter symbol min typ max units notes input leakage current i il -1.0 +1.0 a i/o leakage current ce v ih v cc i io -1.0 +1.0 a output current @ 2.4v i oh -1.0 ma 14 output current @ 0.4v i ol 2.0 ma 14 standby current ce =2.2v i ccs1 200 600 a standby current ce =v cc -0.5v i ccs2 50 150 a operating current i cco1 85 ma write protection voltage (DS1350AB) v tp 4.50 4.62 4.75 v write protection voltage (ds1350y) v tp 4.25 4.37 4.5 v capacitance ( t a = 25 c) parameter symbol min typ max units notes input capacitance c in 510pf input/output capacitance c i/o 510pf
ds1350y/ab 5 of 12 ac electrical (v cc = 5v 5% for DS1350AB) characteristics (t a : see note 10) (v cc = 5v 10% for ds1350y) DS1350AB-70 ds1350y-70 DS1350AB-100 ds1350y-100 parameter symbol min max min max units notes read cycle time t rc 70 100 ns access time t acc 70 100 ns oe to output valid t oe 35 50 ns ce to output valid t co 70 100 ns oe or ce to output active t coe 5 5 ns 5 output high z from deselection t od 25 35 ns 5 output hold from address change t oh 55 ns write cycle time t wc 70 100 ns write pulse width t wp 55 75 ns 3 address setup time t aw 00 ns write recovery time t wr1 t wr2 5 12 5 12 ns 12 13 output high z from we t odw 25 35 ns 5 output active from we t oew 5 5 ns 5 data setup time t ds 30 40 ns 4 data hold time t dh1 t dh2 0 7 0 7 ns 12 13 read cycle see note 1
ds1350y/ab 6 of 12 write cycle 1 see notes 2, 3, 4, 6, 7, 8, and 12 write cycle 2 see notes 2, 3, 4, 6, 7, 8, and 13
ds1350y/ab 7 of 12 power-down/power-up condition battery warning detection see note 14
ds1350y/ab 8 of 12 power-down/power-up timing (t a : see note 10) parameter symbol min typ max units notes v cc fail detect to ce and we inactive t pd 1.5 s 11 v cc slew from v tp to 0v t f 150 s v cc fail detect to rst active t rpd 15 s 14 v cc slew from 0v to v tp t r 150 s v cc valid to ce and we inactive t pu 2ms v cc valid to end of write protection t rec 125 ms v cc valid to rst inactive t rpu 150 200 350 ms 14 v cc valid to bw valid t bpu 1s14 battery warning timing (t a : see note 10) parameter symbol min typ max units notes battery test cycle t btc 24 hr battery test pulse width t btpw 1s battery test to bw active t bw 1s (t a = 25 c) parameter symbol min typ max units notes expected data retention time t dr 10 years 9 warning: under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode. notes: 1. we is high for a read cycle. 2. oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high-impedance state. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t ds are measured from the earlier of ce or we going high. 5. these parameters are sampled with a 5pf load and are not 100% tested. 6. if the ce low transition occurs simultaneously with or latter than the we low transition, the output buffers remain in a high-impedance state during this period. 7. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in high-imped ance state during this period. 8. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high -impedance state during this period.
ds1350y/ab 9 of 12 9. each ds1350 has a built-in switch that disconnects the lithium source until v cc is first applied by the user. the expected t dr is defined as accumulative time in the absence of v cc starting from the time power is first applied by the user. 10. all ac and dc electrical characteristics are valid over the full operating temperature range. for commercial products, this range is 0 c to 70 c. for industrial products (ind), this range is -40 c to +85 c. 11. in a power-down condition the voltage on any pin may not exceed the voltage on v cc . 12. t wr1 and t dh1 are measured from we going high. 13. t wr2 and t dh2 are measured from ce going high. 14. rst and bw are open drain outputs and cannot source cu rrent. external pull-up resistors should be connected to these pins for proper operation. both pins will sink 10ma. 15. ds1350 modules are recognized by underwriters laboratory (u.l. ? ) under file e99151. dc test conditions ac test conditions outputs open output load: 100pf + 1ttl gate cycle = 200ns for operating current input pulse levels: 0 ? 3.0v all voltages are referenced to ground timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5ns ordering information ds1350 ttp - sss - iii operating temperature range blank: 0 to 70 ind: -40 to +85 c access speed 70: 70ns 100: 100ns package type p: 34-pin powercap module v cc tolerance ab: 5% y: 10%
ds1350y/ab 10 of 12 ds1350y/ab nonvolatile sram, 34-pin powercap module inches pkg dim min nom max a 0.920 0.925 0.930 b 0.980 0.985 0.990 c - - 0.080 d 0.052 0.055 0.058 e 0.048 0.050 0.052 f 0.015 0.020 0.025 g 0.020 0.025 0.030
ds1350y/ab 11 of 12 ds1350y/ab nonvolatile sram, 34-pin powercap module with powercap inches pkg dim min nom max a 0.920 0.925 0.930 b 0.955 0.960 0.965 c 0.240 0.245 0.250 d 0.052 0.055 0.058 e 0.048 0.050 0.052 f 0.015 0.020 0.025 g 0.020 0.025 0.030 assembly and use reflow soldering dallas semiconductor recommends that powercap module bases experience one pass through solder reflow oriented labe l-side up (live-bug). hand soldering and touch-up do not touch soldering iron to leads for more than 3 seconds. to solder, apply flux to the pad, heat the lead frame pad and apply solder. to remove part, apply flux, heat pad until solder reflows, and use a solder wick. lpm replacement in a socket to replace a low profile module in a 68-pin plcc socket, attach a ds9034pc powercap to a module base then insert the complete module into the so cket one row of leads at a time, pushing only on the corners of the cap. never apply force to the center of the device. to remove from a socket, use a plcc extraction tool and ensure that it does not hit or da mage any of the module ic components. do not use any other tool for extraction.
ds1350y/ab 12 of 12 recommended powercap module land pattern inches pkg dim min nom max a - 1.050 - b - 0.826 - c - 0.050 - d - 0.030 - e - 0.112 - recommended powercap module solder stencil inches pkg dim min nom max a - 1.050 - b - 0.890 - c - 0.050 - d - 0.030 - e - 0.080 -

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